CVE-2024-24853

Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

CVSS v3 7.2 HIGH

7.2^/10

CVSS v3 : HIGH

Vector :

Exploitability : 0.6 / Impact : 6.0

Attack Vector LOCAL

Attack Complexity HIGH

Privileges Required HIGH

User Interaction REQUIRED

Confidentiality Impact HIGH

Integrity Impact HIGH

Availability Impact HIGH

Scope CHANGED

References

Link	Resource
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html

Configurations

No configuration.

History

15 Apr 2026, 00:35

Type	Values Removed	Values Added
Summary		(es) El orden de comportamiento incorrecto en la transición entre el monitor ejecutivo y el monitor de transferencia SMI (STM) en algunos procesadores Intel(R) puede permitir que un usuario privilegiado habilite potencialmente la escalada de privilegios a través del acceso local.

14 Aug 2024, 14:15

Type	Values Removed	Values Added
New CVE

Information

Published : 2024-08-14 14:15

Updated : 2026-04-15 00:35

NVD link : CVE-2024-24853

Mitre link : CVE-2024-24853

CVE.ORG link : CVE-2024-24853

JSON object : View

Products Affected

No product.

CWE

CWE-696

Incorrect Behavior Order

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