CVE-2026-29643

XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.
Configurations

No configuration.

History

21 Apr 2026, 20:16

Type Values Removed Values Added
References () https://github.com/OpenXiangShan/XiangShan/issues/3959 - () https://github.com/OpenXiangShan/XiangShan/issues/3959 -
CVSS v2 : unknown
v3 : unknown
v2 : unknown
v3 : 7.1
CWE CWE-703

20 Apr 2026, 22:16

Type Values Removed Values Added
New CVE

Information

Published : 2026-04-20 22:16

Updated : 2026-04-21 20:16


NVD link : CVE-2026-29643

Mitre link : CVE-2026-29643

CVE.ORG link : CVE-2026-29643


JSON object : View

Products Affected

No product.

CWE
CWE-703

Improper Check or Handling of Exceptional Conditions