A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as "writes preserve values, reads ignore values," i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.
References
Configurations
No configuration.
History
21 Apr 2026, 20:16
| Type | Values Removed | Values Added |
|---|---|---|
| CWE | CWE-1244 | |
| CVSS |
v2 : v3 : |
v2 : unknown
v3 : 7.8 |
20 Apr 2026, 21:16
| Type | Values Removed | Values Added |
|---|---|---|
| New CVE |
Information
Published : 2026-04-20 21:16
Updated : 2026-04-21 20:16
NVD link : CVE-2026-29642
Mitre link : CVE-2026-29642
CVE.ORG link : CVE-2026-29642
JSON object : View
Products Affected
No product.
CWE
CWE-1244
Internal Asset Exposed to Unsafe Debug Access Level or State
