An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
References
| Link | Resource |
|---|---|
| https://developer.arm.com/documentation/111823 | Vendor Advisory |
Configurations
Configuration 1 (hide)
| AND |
|
History
20 Apr 2026, 12:53
| Type | Values Removed | Values Added |
|---|---|---|
| First Time |
Arm c1-pro Firmware
Arm c1-pro Arm |
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| Summary |
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| References | () https://developer.arm.com/documentation/111823 - Vendor Advisory | |
| CPE | cpe:2.3:h:arm:c1-pro:-:*:*:*:*:*:*:* cpe:2.3:o:arm:c1-pro_firmware:*:*:*:*:*:*:*:* |
02 Mar 2026, 17:16
| Type | Values Removed | Values Added |
|---|---|---|
| CVSS |
v2 : v3 : |
v2 : unknown
v3 : 3.6 |
02 Mar 2026, 15:16
| Type | Values Removed | Values Added |
|---|---|---|
| New CVE |
Information
Published : 2026-03-02 15:16
Updated : 2026-04-20 12:53
NVD link : CVE-2026-0995
Mitre link : CVE-2026-0995
CVE.ORG link : CVE-2026-0995
JSON object : View
Products Affected
arm
- c1-pro
- c1-pro_firmware
CWE
CWE-362
Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
