An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
References
| Link | Resource |
|---|---|
| https://developer.arm.com/documentation/111823 |
Configurations
No configuration.
History
02 Mar 2026, 17:16
| Type | Values Removed | Values Added |
|---|---|---|
| CVSS |
v2 : v3 : |
v2 : unknown
v3 : 3.6 |
02 Mar 2026, 15:16
| Type | Values Removed | Values Added |
|---|---|---|
| New CVE |
Information
Published : 2026-03-02 15:16
Updated : 2026-03-02 20:29
NVD link : CVE-2026-0995
Mitre link : CVE-2026-0995
CVE.ORG link : CVE-2026-0995
JSON object : View
Products Affected
No product.
CWE
CWE-362
Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
