CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Configurations

Configuration 1 (hide)

cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*

History

05 Feb 2026, 15:25

Type Values Removed Values Added
First Time Chipsalliance rocketchip
Chipsalliance
Summary
  • (es) Se descubrió una vulnerabilidad en RISC-V Rocket-Chip v1.6 y versiones anteriores, donde la instrucción SRET (Supervisor-mode Exception Return) no logra transicionar correctamente el nivel de privilegio del procesador. En lugar de bajar de categoría desde el modo Máquina (M-mode) a modo Supervisor (S-mode) según lo especificado por el bit sstatus.SPP, el procesador permanece incorrectamente en M-mode, lo que lleva a una vulnerabilidad crítica de retención de privilegios.
References () https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET - () https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET - Exploit, Third Party Advisory
References () https://github.com/chipsalliance/rocket-chip.git - () https://github.com/chipsalliance/rocket-chip.git - Product
CPE cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*

12 Nov 2025, 21:15

Type Values Removed Values Added
CVSS v2 : unknown
v3 : unknown
v2 : unknown
v3 : 6.5
CWE CWE-266

10 Nov 2025, 20:15

Type Values Removed Values Added
New CVE

Information

Published : 2025-11-10 20:15

Updated : 2026-02-05 15:25


NVD link : CVE-2025-63384

Mitre link : CVE-2025-63384

CVE.ORG link : CVE-2025-63384


JSON object : View

Products Affected

chipsalliance

  • rocketchip
CWE
CWE-266

Incorrect Privilege Assignment