A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
References
| Link | Resource |
|---|---|
| https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET | Exploit Third Party Advisory |
| https://github.com/chipsalliance/rocket-chip.git | Product |
Configurations
History
05 Feb 2026, 15:25
| Type | Values Removed | Values Added |
|---|---|---|
| First Time |
Chipsalliance rocketchip
Chipsalliance |
|
| Summary |
|
|
| References | () https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET - Exploit, Third Party Advisory | |
| References | () https://github.com/chipsalliance/rocket-chip.git - Product | |
| CPE | cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:* |
12 Nov 2025, 21:15
| Type | Values Removed | Values Added |
|---|---|---|
| CVSS |
v2 : v3 : |
v2 : unknown
v3 : 6.5 |
| CWE | CWE-266 |
10 Nov 2025, 20:15
| Type | Values Removed | Values Added |
|---|---|---|
| New CVE |
Information
Published : 2025-11-10 20:15
Updated : 2026-02-05 15:25
NVD link : CVE-2025-63384
Mitre link : CVE-2025-63384
CVE.ORG link : CVE-2025-63384
JSON object : View
Products Affected
chipsalliance
- rocketchip
CWE
CWE-266
Incorrect Privilege Assignment
